Emulation of Scan Paths in Sequential Circuit Synthesis

Scan paths an: generally added to a sequential cileuit in a final design for testability step. We present an approach to incorporate the behavior of a scan path during circuit synthesis. thus avoiding to implement the scan path shift register as a separate structural entity. The shift transitions of the scan path an: trcalCd as a pan of the system functionality. Depending on the minimization strategy for the system logic. either the delay or the area of the ciIcuit can be reduced compared to a conventional scan path. which may be interpreted as a special case of realizing the combinational logic. The approach is also extended to partial scan paths. It is showe that the resulting structure is fully testable and test pallerns can be efficienUy produced by a combinational test generator. The advantages of the approach arc illustrated with a collection of finite state machine examples.